@Article{JICS-2-66,
author = {},
title = {Multi-level Sequential Circuit Partitioning for Delay Minimization of VLSI Circuits},
journal = {Journal of Information and Computing Science},
year = {2024},
volume = {2},
number = {1},
pages = {66--70},
abstract = { Sequential  graph  partitioning  algorithms  have  been  developed  to  fulfill  the  requirements  of 
emerging multi-phase problems in circuit delay models. In this paper we propose a heuristic algorithm for k-
partition,  which  minimizes  the  circuit  delay  and  cut  size.  Experimental  results  with  MCNC  benchmark 
circuits have shown that the delay in the circuit can be reduced by marginally in comparison with the other 
algorithms [2,3,11]. 
},
issn = {1746-7659},
doi = {https://doi.org/},
url = {http://global-sci.org/intro/article_detail/jics/22822.html}
}